The present invention relates to the soldering of different types of chips to multi-chip module substrates and more particularly to joining to the same substrate of both chips requiring high temperature reflow and materials and/or techniques and those requiring low temperature reflow materials and/or techniques.
The joining to the same ceramic module substrate both chips using high temperature reflow techniques, such as CMOS 7S ASIC, C4 flip-chips, and those chips, such as the thin small outline package (TSOP) chips and plastic ball grid array (PBGA) chips, using low temperature reflow techniques is difficult and expensive. First of all, the chip joining of the variuous chips cannot be performed at the very same time because the use of the high temperature reflow techniques for C4 chips would destroy TSOP and/or PBGA chips. In addition, when the high temperature C4 joining process is performed first, upon completion of that process, the chip carrier surface is no longer flat interfering with the use of conventional paste screening processes on TSOP pads. Furthermore, the space between the various chips on the substrate surface is close (in some cases less than 1.5 mm) making paste screening of the eutectic paste with acceptable yields virtually impossible using present pastes.
The modules are expensive and the correction of errors occurring in post C4 chip processing without damaging the module during rework is a serious problem with present rework techniques. First of all, the above mentioned close spacing makes removal of a chip without damaging the chip site and/or adjacent chips or their connections difficult using present chip removal tools and techniques. In addition, solder sucking types of tools are ineffective to remove the solder because of heat that the ceramic absorbs, and traditional copper block dressing techniques do not dress the chip site properly because they do not have enough mass to apply constant pressure to the chip site during the copper dress operation in the furnace.
Therefore, is it an object of the present invention to provide a new method and apparatus of joining different types of chips with different physical characteristics to a common chip carrier surface.
Another object of the present invention is to provide a new method and apparatus for reworking modules populated chips with different physical characteristics.
In accordance with the present invention, the chips requiring high temperature reflow for attachment to a module substrate are attached first and then a eutectic water soluble solder paste and/or water soluble flux is dispensed on both the TSOP and the PBGA chip pads instead of using the paste screening techniques. The dispensing is done by injecting solder paste on the solder sites individually. Characteristics of the solder paste used is that it must be fluid enough to be injected onto the individual sites yet have enough body that it remains in place and does not run from site to site once dispensed. A paste capable of providing such characteristics is one having: a) a very fine particle size in the range of 400 to 500 mesh and preferably between 400 and 450 mesh; b) a low viscosity (below 500 k centipoise and preferably between 425 to 375 cps); and c) a solid content of 86% or lower and preferably between 84 and 80%. The chips to be joined to the module using low temperature module joining are then placed on the module substrate surface and then put in an oven for reflow to attach these chips to the surface. After the joining process, the modules are cleaned by spraying deionized water on them to remove any flux or solder residues and the modules are electrically tested to determine if the joining process has resulted in connection with the proper mechanical and electrical characteristics.
When errors are detected during testing in any of the chips mounted on the module with the low temperature joining process, those chips can be removed by attaching a magnetically attracted element to their surface, suspending a magnetic over the chip and the element and then reheating the module to cause reflow of the solder. Upon reflow of the solder, the magnetic lifts the chip with the magnetically attracted element off the surface of the module allowing redressing of the chip site and reuse of the module with a replacement chip.
The use of this magnetic pulling technique eliminates spacing concerns normally encountered with a pulling device. The magnetic pull forces produced are predictable and create a smooth acceleration during separation of the chip from the substrate. This device can also be applied to removing xe2x80x9cfine pitchxe2x80x9d C4 devices at higher temperatures. As chip footprints increase in size, so does the force that is required to remove the chips. The magnetic pulling has the advantage of a ever-present shearing force which acts on the interconnection only when the solder liquefies. This process can be adapted to present manufacturing auer boats (multiple substrate holders or other reflow fixturing).
Once certain chips, such as PBGA chips, have been removed, a large residual solder volume is left on the ceramic surface. To remove this solder, spring pressure is applied to the top of a copper block to allow the block to fully dress the site. The spring forces are used to assure proper contact between the copper block and the residual solder balls though the solder balls may vary in height to guarantee reducing solder on the module surface to an acceptable level.